The present disclosure relates to semiconductor device design, manufacture and packaging methods to improve electrical current delivery into a semiconductor chip.
Flip chip generally uses the Controlled Collapse Chip Connection or, C4, technology to interconnect semiconductor devices of IC chips or Microelectromechanical systems (MEMS), or alternatively, the chip die, to packages for connection to external circuitry with solder bumps that have been deposited onto the chip pads. Power (i.e., power and ground) and signals have to be delivered to die from package through these C4 connectors or “bumps”.
Like other interconnects, C4 bumps are susceptible to electromigration and the susceptibility is strongly affected by the amount of current carried by the bumps. According to the Black's equation, the mean-time-to-failure of the bumps is a power of their current density. This means that reducing the amount of current carried by the bumps significantly lowers their susceptibility to electromigration. Thus, there is a limit as to how much current each C4 bump can carry and this limit must be managed to meet target chip lifetime.
The current density of C4 bumps is determined by two factors: the amount of current carried by the bumps and the dimension of the bumps. The amount of current carried by the bumps has increased, as the current drawn per unit area has increased due to high transistor integration (by aggressive technology scaling) and high clock frequency. Recently, nominal clock frequency tends to saturate but most microprocessor chips enable a frequency boost mode in which most cores are turned off and the frequency of one or only a few cores is boosted for better single-thread performance. The boost mode prevents total chip power from increasing by turning off most cores, but it causes high power dissipated or high current drawn in the boosted region of the chip. As a result, the concern of excessive C4 current remains. The dimension of C4 bumps between package substrates and chips has been slightly shrunk, but emerging 3D integration technology has introduced much smaller C4 bumps to bond the chips stacked vertically. In addition to smaller dimensions, the so-called mini or micro bumps need to carry current drawn by one or multiple chips in the stack. As a result, the effective current density of these bumps increases significantly.
In addition to the current density concern, the susceptibility of the C4 bumps to electromigration increases if the bumps are lead-free due to “green” regulations. The lead-free bumps are reportedly more vulnerable to electromigration than the traditional ones by creating non-uniform current distribution in the bumps. As a result, the current limit of lead-free bumps is set significantly lower than that of the traditional bumps in order to achieve the same chip lifetime. The challenging limit makes it even more critical to consider C4 current awareness in designing microprocessor chips and packages.
C4 current limit may be set by the target electromigration lifetime governed by several key factors. As shown in FIG. 1, key factors 10 that effect C4 lifetime electromigration reliability 11 include: C4 technologies 12 (e.g., lead-free, design structure/mechanics, pad shape/structure); C4 operating currents 14, and C4 operating temperatures 16—all which effect electromigration reliability of the chip over time. Factors effecting C4 operating currents include the amount of current drawn by integrated circuit devices 14a on the chip or die, the density and location of the C4 bumps 14c, and the power grid networks 14b that connect the devices and the C4 bumps. That is, the power dissipated or current drawn by the devices is delivered from the package pins through substrate wires therein through the C4 connections (bumps) to distribute current to the chip die through one or multiple chip wiring levels. Thus, current delivery design factors include the amount of current drawn by and the location of operating devices at the die, how they are wired (designed power grid between C4s and devices), and how many C4s are populated in a unit area and how they are placed, all effect C4 current draw and ultimately chip reliability susceptible to electromigration.
As described above, in semiconductor chip manufacturing, C4 current limits are becoming difficult to meet due to a variety of factors including: increasing use of Pb-free C4; higher target frequencies of IC chip operation; and frequency boosted modes of operation. As C4 current reduction is critical during chip planning, a system and method that expediently performs integrated circuit current and sensitivity estimation would be highly desirable.
It would also be highly desirable to provide an automated system and method that optimizes semiconductor chip floorplans and C4 bump footprints with respect to current draw through the bumps. However, there are currently no known automated mechanisms that place standard cells composed of devices or higher-level units composed of cells for the balanced current or reliability of C4 bumps.
There are dynamic management mechanisms used in other areas such as power or temperature, but none for current management. Such existing mechanisms may indirectly control the exposure to excessive current delivery, but they cannot directly keep C4 current to be met the limit.
In addition, dynamic current management mechanisms can be coupled with static design methodologies such as C4 current-aware floorplanning and C4 placement optimization in order to improve current delivery into a chip as well as performance.